In this study, we demonstrate near-0.1 V minimum operating voltage of a\nlow-variability Silicon on Thin Buried Oxide (SOTB) process for one million logic gates\non silicon. Low process variability is required to obtain higher energy efficiency during\nultra-low-voltage operation with steeper subthreshold slope transistors. In this study,\nwe verify the decrease in operating voltage of logic circuits via a variability-suppressed\nSOTB process. In our measurement results with test chips fabricated in 65-nm SOTB and\nbulk processes, the operating voltage at which the first failure is observed was lowered\nfrom 0.2 to 0.125 V by introducing a low-variability SOTB process. Even at 0.115 V,\nover 40% yield can be expected as per our measurement results on SOTB test chips.
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